PC-Based Logic Analyzer
Internal Clock (Timing) (Asynchronous): 100Hz~200MHz
External Clock (State) (Synchronous): 100MHz
Bandwidth: 75MHz
Range of the Trigger Voltage: -6V~+6V
Resolution of the Trigger Voltage: ±0.1V
RAM Size: 64Mbits
Memory Depth per Channel: 2Mbits (Max 512Mbits for compression)
Trigger Mode: Pattern/Edge
Trigger Channel: 16 CH
Post-Trigger: YES
Trigger Level: 1 Level
Trigger Count: 1~65535
Debug and Analysis Considerations for Optimizing Signal Integrity
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Sampling Frequency :
Test Signal :
Memory :
Trigger :
Electric Specification:
| Item | Min | Typical | Max |
| Working Voltage | 4.5V | 5V | 5.5V |
| Current Consumption at Rest | - | - | 200mA |
| Current Consumption at Work | - | - | 400mA |
| Power Consumption at Rest | - | - | 1W |
| Power Consumption at Work | - | - | 2W |
| Error in Phase Off | - | - | 1.5ns |
| Vinput of Testing Channel | -30V | - | +30V |
| Reference Voltage | -6V | - | +6V |
| Input Resistance | - | 500KΩ/10pf | - |
| Working Temperature | 5℃ | - | 70℃ |
| Storage Temperature | -40℃ | - | 80℃ |
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=============================================================== Debug and Analysis Considerations for Optimizing Signal Integrity
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